This invention relates to a booster circuit contained in a semiconductor device and, more particularly, to a booster circuit used as an internal power supply for a dynamic random access memories (DRAM) for use in a portable apparatus driven by an external power supply of 1.8V and a driving method thereof.
Generally, a booster circuit of the type described (which will be called hereafter xe2x80x9ca normal pump circuitxe2x80x9d) comprises a pump capacitor, switches, and a power supply. The normal pump circuit has a current (charge) efficiency of about 50%.
In order to realize a low power consumption, a booster circuit (a pump circuit) having an improved current (charge) efficiency more than 50% is described or disclosed in Japanese Unexamined Patent Publication Tokkai No. Hei 9-231,752 or JP-A 9-231752. The booster circuit (pump circuit) disclosed in JP-A 9-231752 comprises two pump capacitors and five switches.
In the manner which will later be described in conjunction with FIGS. 1A and 1B, the booster circuit disclosed in JP-A 9-231752 comprises a first pump capacitor, a second pump capacitor, and first through fifth switches. The booster circuit is supplied with a power-supply voltage (power-supply potential) and a ground voltage (ground potential). The booster circuit produces (generates) a boosted level (boosted potential). That is, the booster circuit has a node supplied with the power-supply voltage, a node supplied with the ground voltage, and a node for generating the boosted level. The node supplied with the power-supply voltage is called a xe2x80x9cpower-supply nodexe2x80x9d. The node supplied with the ground voltage is called a xe2x80x9cground nodexe2x80x9d. The node for generating the boosted level is called a xe2x80x9cbooster nodexe2x80x9d. In addition, the booster circuit has first and second input nodes and first and second intermediate nodes.
The first pump capacitor is connected between the first input node and the first intermediate node. The second pump capacitor is connected between the second input node and the second intermediate node.
The first through the third switches are connected in series between the power-supply node and the ground node. Specifically, the first switch is connected between the power-supply node and the first input node. Generally, the first switch comprises a P-channel metal oxide semiconductor (PMOS) transistor which has a source connected to the power-supply node and a drain connected to the first input node. The second switch is connected between the first input node and the second input node. Generally, the second switch comprises an N-channel metal oxide semiconductor (NMOS) transistor which has a drain connected to the first input node and a source connected to the second input node. The third switch is connected between the second input node and the ground node. Generally, the third switch comprises an NMOS transistor which has a drain connected to the second input node and a source connected to the ground node.
The fourth switch has a fixed contact fixedly connected to the first intermediate node and a moving contact which is selectively connected to either the power-supply node or the booster node. The fifth switch has a fixed contact fixedly connected to the second intermediate node and a moving contact which is selectively connected to either the power-supply node or the booster node.
The booster circuit having such structure repeats a first state and a second state to realize high efficiency of booster and a supply current. The first state is a state where the first pump capacitor discharges and the second pump capacitor is charged. On the other hand, the second state is a state where the first pump capacitor is charged and the second pump capacitor discharges.
More specifically, in the first state, the first switch is turned on or makes, the second switch is turned off or breaks, the third switch is turned on or makes, the fourth switch connects the first intermediate node with the booster node, and the fifth switch connected the second intermediate node with the power-supply node. In this state, the first pump capacitor is climbed by the power-supply voltage to supply the booster node with a current. Simultaneously, the second pump capacitor is charged by the power-supply voltage and the ground voltage.
On the other hand, in the second state, the first switch is turned off or breaks, the second switch is turned on or makes, the third switch is turned off or breaks, the fourth switch connects the first intermediate node with the power-supply node, and the fifth switch connects the second intermediate node with the booster node. In this state, the first and the second pump capacitors are connected to each other in series, the first pump capacitor is climbed by the power-supply voltage, and a current flows from the second pump capacitor to the booster node. In this event, inasmuch as the first pump capacitor has an electrode direction in the opposite direction to a booster direction, the first pump capacitor is charged with charges moved.
It is assumed that the amount of charges moving for a half cycle per capacitor is represented by xcex94Q. In this event, the amount of charges flowing out of the power-supply node is equal to 3 xcex94Q. On the other hand, the amount of charges supplied to the booster node is equal to 2 xcex94Q. Accordingly, the booster circuit has a current (charge) efficiency of about 66.6% or two-thirds. In comparison with the normal pump circuit having the current (charge) efficiency of about 50%, the booster circuit has an improved current (charge) efficiency about 1.33 times.
However, the above-mentioned booster circuit disclosed in JP-A 9-231752 is disadvantageous in that a voltage enable to boost is limited to 1.5 times the power-supply voltage. Therefore, a supply current drastically decreases when the boosted level approaches 1.3 times the power-supply voltage and a supply efficiency deteriorates. A ground occurring this problem will later be described in conjunction with FIG. 2.
In addition, various booster circuits except for the above-mentioned one are proposed. By way of example, WO98/44621 discloses a power-supply circuit which is capable of variably controlling a boosting ratio by means of two pump capacitors and five switches. More specifically, a power course circuit can reduce its own power consumption and can select its boosting ratio in accordance with the duty ratio. The power source circuit comprises a charge pump circuit including a first switching section which accumulates charges in a first capacitor and a second switching section which transfers the charges accumulated in the first capacitor to a second capacitor, and a circuit which generates switching signals for controlling the first and the second switching sections. The first switching section comprises first and second switching elements which are respectively connected to different potentials on one side and to one end of the first capacitor on the other side. The switching signal generating circuit variably controls the boosting rate by turning on or off the first switching element and turning off the second switching element or by turning on or off the second switching element and turning off the first switching element. The potential of the switching signal when the first and the second switching elements are turned off is made equal to the potential supplied to the source of a switching transistor. The boosting rate is controlled in accordance with the duty ratio when a liquid crystal display is operated for partial display.
U.S. Pat. No. 6,259,612 issued to Yasuo Itoh discloses a semiconductor integrated circuit having a small chip area using two pump capacitors. According to Itoh, an internal voltage generator generates an internal voltage that is obtained by up-converting or down-converting an external power supply voltage. A resistor-voltage divider, having a plurality of resistors, outputs a first divided voltage that is obtained by dividing the internal voltage according to a resistance ratio of the resistors. A capacitor-voltage divider, having a plurality of capacitors connected in series between an output terminal of the internal voltage generator and a ground level, outputs a second divided voltage from the capacitors. A comparator compares a reference voltage and the first divided voltage for controlling the internal voltage generator according to a result of comparison. The comparator judges whether to halt operation of the internal voltage generator or not based on the result of comparison between the reference voltage and the first divided voltage while the internal voltage generator is operating. On the other hand, the comparator operates the internal voltage generator based on the result of comparison between the reference voltage and the second divided voltage while the internal voltage generator is not operating. The comparator further controls the resistor-voltage divider to that a current flows therethrough only when the internal voltage generator is operating.
U.S. Pat. No. 5,774,012 issued to Heung-Soo Im discloses a high-efficient charge-pumping circuit using two pump capacitors and three switches. According to Im, a charge-pumping circuit of a semiconductor memory device generates a voltage higher than an applied supply voltage. The charge-pumping circuit includes a first MOS transistor having gate and drain terminals between through which the supply voltage is received and a source terminal through which an initial voltage is provided to a first mode. A first capacitor with predetermined capacitance has one plate connected to the first node and the other plate through which an applied first oscillating signal is received. A third MOS transistor has gate and source terminals connected to the first node to introduce the electric current of the first node into its drain terminal. A second capacitor with capacitance lower than that of the first capacitor has one plate connected to the second node that is the drain terminal of the third MOS transistor and the other plate through which an applied second oscillating signal is received. A second MOS transistor has drain and gate terminals connected to the first node and the second node, respectively, and a source terminal connected to an output terminal so as to apply the voltage of the first node to the output terminal in response to the voltage of the second node.
Japanese Unexamined Patent Publication Tokkai No. Hei 9-238,463 or JP-A 9-238463 discloses a high-efficient charge pump circuit using two pump capacitors and four switches. More specifically, this circuit comprises a reference voltage generator circuit which generates three voltage VH, V2, and V1. A saw-tooth wave generating circuit generates saw-tooth waves with the voltage VH. First and second comparators compare the voltages V1 and V2 with the saw-tooth wave output from the saw-tooth wave generating circuit and then generate control signals. Second, third, fifth and sixth transistors turn on according to the control signals of the first and the second comparators and then connect the minus sides of first and second capacitors to the power supply. First and second current supply circuit supply base current to the third and the sixth transistors according to the control signals of the first and the second comparators. With this structure, a control can be done easily.
Another example is disclosed in an article which is contributed by Takeshi Hamamoto at al. to IEEE 1996 Symposium on VLSI Circuits Digest of Technical Papers, pages 110-111, and which has a title of xe2x80x9cAn Efficient Charge Recycle and Transfer Pump Circuit for Low Operating Voltage DRAMs.xe2x80x9d
It is therefore an object of this invention to provide a booster circuit and a driving method thereof, which are capable of increasing a current supply efficiency in accordance with a boosted level with demerit in an area kept within two times.
It is another object of this invention to provide a booster circuit of the type described and a driving method thereof, which are capable of switching between a conventional mode and a low consumption current mode.
Other objects of this invention will become clear as the description proceeds.
On describing the gist of an aspect of this invention, it is possible to be understood that a booster circuit has a power-supply node supplied with a power-supply voltage, a ground node supplied with a ground voltage, a booster node for generating a booster level, first and second input nodes, and first and second intermediate nodes. The booster circuit comprises a first pump capacitor connected between the first input node and the first intermediate node and a second pump capacitor connected between the second input node and the second intermediate node.
According to a first aspect of this invention, the above-understood booster circuit comprises first through fifth switches. The first switch has a first fixed contact fixedly connected to the first input node and a first moving contact which is selectively connected to one of the power-supply node, the ground node, and the booster node. The second switch has a second fixed contact fixedly connected to the second input node and a second moving contact which is selectively connected to one of the power-supply node, the ground node, and the booster node. The third switch has a third fixed contact and a third moving contact disposed between the first and the second intermediate nodes. The third switch makes or breaks between the first and the second intermediate nodes. The fourth switch has a fourth fixed contact fixedly connected to the first intermediate node and a fourth moving contact which is selectively connected to one of the power-supply node, the booster node, and a non-connective node connected to nowhere. The fifth switch has a fifth fixed contact fixedly connected to the second intermediate node and a fifth moving contact which is selectively connected to one of the power-supply node, the booster node, and the non-connective node.
In the first aspect of this invention, a driving method drives the above-understood booster circuit at a low consumption current mode which repeatedly puts the booster circuit into first through fourth low consumption states. At the first low consumption state, the first switch connects the first input node with the ground node, the second switch connects the second input node with the power-supply node, the third switch breaks, the fourth switch connects the first intermediate node with the power-supply node, and the fifth switch connects the second intermediate node with the booster node. At the second low consumption state, the first switch connects the first input node with the power-supply node, the second switch connects the second input node with the booster node, the third switch makes, the fourth switch connects the first intermediate node with the non-connective node, and the fifth switch connects the second intermediate node with the non-connective node. At the third low consumption state, the first switch connects the first input node with the power-supply node, the second switch connects the second input node with the ground node, the third node breaks, the fourth switch connects the first intermediate node with the booster node, and the fifth switch connects the second intermediate node with the power-supply node. At the fourth low consumption state, the first switch connects the first input node with the booster node, the second switch connects the second input node with the power-supply node, the third switch makes, the fourth switch connects the first intermediate node with the non-connective node, and the fifth switch connects the second intermediate node with the non-connective node.
In the first aspect of this invention, a driving method drives the above-understood booster circuit at a conventional mode which repeatedly puts the booster circuit into first and second conventional states. At the first conventional state, the first switch connects the first input node with the ground node, the second switch connects the second input node with the power-supply node, the third switch breaks, the fourth switch connects the first intermediate node with the power-supply node, and the fifth switch connects the second intermediate node with the booster node. At the second conventional state, the first switch connects the first input node with the power-supply node, the second switch connects the second input node with the ground node, the third switch breaks, the fourth switch connects the first intermediate node with the booster node, and the fifth switch connects the second intermediate node with the power-supply node.
According to a second aspect of this invention, the above-understood booster circuit comprises a connection line and first through fourth switches. The connection line extends between the vicinity of the first input node and the vicinity of the second input node. The first switch has a first fixed contact fixedly connected to the first input node and a first moving contact which is selectively connected to one of the power-supply node, the ground node, and the connection line. The second switch has a second fixed contact fixedly connected to the second input node and a second moving contact which is selectively connected to one of the power-supply node, the ground node, and the connection line. The third switch has a third fixed contact fixedly connected to the first intermediate node and a third moving contact which is selectively connected to either the booster node or the power-supply node. The fourth switch has a fourth fixed contact fixedly connected to the second intermediate node and a fourth moving contact which is selectively connected to either the booster node or the power-supply node.
In the second aspect of this invention, a driving method drives the above-understood booster circuit at a low consumption current mode which repeatedly puts the booster circuit into first through fourth low consumption states. At the first low consumption state, the first switch connects the first input node with the power-supply node, the second switch connects the second input node with the ground node, the third switch connects the first intermediate node with the booster node, and the fourth switch connects the second intermediate node with the power-supply node. At the second low consumption state, the first switch connects the first input node with the connection line, the second switch connects the second input node with the connection line, the third switch connects the first intermediate node with the power-supply node, and the fourth switch connects the second intermediate node with the booster node. At the third low consumption state, the first switch connects the first input node with the ground node, the second switch connects the second input node with the power-supply node, the third switch connects the first intermediate node with the power-supply node, and the fourth switch connects the second intermediate node with the booster node. At the fourth low consumption state, the first switch connects the first input node with the connection line, the second switch connects the second input node with the connection line, the third switch connects the first intermediate node with the booster node, and the fourth switch connects the second intermediate node with the power-supply node.
In the second aspect of this invention, a driving method drives the above-understood booster circuit at a conventional mode which repeatedly puts the booster circuit into first and second conventional states. At the first conventional state, the first switch connects the first input node with the power-supply node, the second switch connects the second input node with the ground node, the third switch connects the first intermediate node with the booster node, and the fourth switch connects the second intermediate node with the power-supply node. At the second conventional state, the first switch connects the first input node with the ground node, the second switch connects the second input node with the power-supply node, the third switch connects the first intermediate node with the power-supply node, and the fourth switch connects the second intermediate node with the booster node.